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Ordering number : ENA1435
LE25LB2562M
Overview
256Kbit Serial SPI EEPROM (SPI Bus)
The LE25LB2562M is a 256Kbit EEPROM that supports serial peripheral interface (SPI). It realizes high speed operation and high level reliability by incorporating SANYO's high performance CMOS EEPROM technology. The interface is compatible with SPI bus protocol, therefore, it is best suited for applications that require small-scale rewritable nonvolatile parameter memory. Moreover, the LE25LB2562M has a 64 bytes page rewrite function that provides rapid data rewriting.
Features
* Capacity * Single supply voltage * Serial interface * Operating clock frequency * Low current dissipation * Page write function * Rewrite time * Number of rewrite times * Data retention period * High reliability : 256Kbits (32Kx8bits) : 1.8V to 3.6V : SPI Mode0, Mode3 supported : 5MHz (2.5V to 3.6V), 3MHz (1.8V to 3.6V) : Standby : 3A (max.) : Active (Read) : 1mA (max.) : Active (Rewrite) : 3mA (max.) : 64bytes : 10ms : 106 times : 20years : Adopts SANYO's proprietary symmetric memory array configuration (USP6947325) Incorporates a feature to prohibit write operations under low voltage conditions.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
40809 SY /20090309-S00004 No.A1435-1/14
LE25LB2562M
Package Dimensions
unit : mm (typ) 3032D [LE25LB2562M]
5.0 8 5
4.4 6.4
1 (0.65) 1.27
4 0.35 0.15
SANYO : MFP8(225mil)
Packages
MFP8 (225mil) : LE25LB2562M Pin Descriptions
PIN.1 PIN.2 CS SO WP VSS SI SCK HOLD VDD Chip select Serial data output Write protect Ground Serial data input Serial clock Hold Power supply
Pin Assignment
0.1
(1.5)
1.7max
0.63
CS SO WP VSS
1 2 3 4
8 7 6 5
VDD HOLD SCK SI
PIN.3 PIN.4 PIN.5 PIN.6 PIN.7 PIN.8
Block Diagram
ADDRESS BUFFERS & LATCHES
XDECODER
EEPROM Cell Array
Y-DECODER
CONTROL LOGIC
I/O BUFFERS & DATA LATCHES
SERIAL INTERFACE
CS
SCK
SI
SO
WP
HOLD
No.A1435-2/14
LE25LB2562M
Specifications
Absolute Maximum Rating/If an electrical stress exceeding the maximum rating is applied, the device may be damaged.
Parameter Storage temperature Supply voltage DC input voltage Overshoot voltage (below 20ns) Symbol Conditions Ratings -65 to +150 -0.5 to 4.6 -0.5 to VDD+0.5 -1.0 to VDD+0.5 Unit C V V V
Operating Conditions
Parameter Operating temperature Operating supply voltage Symbol Conditions Ratings -40 to +85 1.8 to 3.6 Unit C V
DC Electrical Characteristics
Parameter Supply current when reading Symbol ICCR Conditions CS = 0.1VDD, HOLD = WP = 0.9VDD SI = 0.1VDD/0.9VDD, SO = Open Operating frequency = 5MHz, VDD = 3.6V CS = 0.1VDD, HOLD = WP = 0.9VDD SI = 0.1VDD/0.9VDD, SO = Open Operating frequency = 5MHz, VDD = 2.5V CS = 0.1VDD, HOLD = WP = 0.9VDD SI = 0.1VDD/0.9VDD, SO = Open Operating frequency = 3MHz, VDD = 1.8V Supply current when writing CMOS standby current ICCW ISB VDD = VDD max., VIN = 0.1VDD/0.9VDD CS = VDD, VIN = VDD or VSS VDD = 3.6V CS = VDD, VIN = VDD or VSS VDD = 2.5V Input leakage current Output leakage current Input low voltage Input high voltage Output low voltage ILI ILO VIL VIH VOL1 VOL2 Output high voltage VOH1 VOH2 VIN = VSS to VDD, VDD = VDD max. VIN = VSS to VDD, VDD = VDD max. VDD = VDD max. VDD = VDD min. IOL = 3.0mA, VDD = 2.5V to 3.6V IOL = 0.7mA, VDD = 1.8V to 3.6V IOH = -0.4mA, VDD = 2.5V to 3.6V IOH = -0.1mA, VDD = 1.8V to 3.6V 0.8VDD 0.8VDD -2 -2 -0.3 0.7VDD 2 2 0.3VDD VDD+0.3 0.4 0.2 A A V V V V V V 2 A 3 3 mA A 0.3 mA 0.5 mA min typ max 1 Unit mA
Capacitance at Ta = 25C, f = 1.0MHz
Parameter Output pin capacitance Input pin capacitance Symbol CDQ CIN VDQ = 0V VIN = 0V Conditions min typ max 12 6 Unit pF pF
Note : These parameters are sampled and not 100% tested.
AC Electrical Characteristics
Input pulse level Input pulse rise/fall time Output detection voltage Output load 0.2xVDD to 0.8xVDD 10ns 0.5xVDD 30pF
No.A1435-3/14
LE25LB2562M
AC Characteristics (at FCLK = 5MHz)/VDD = 2.5V to 3.6V
Parameter Clock frequency SCK logic high level pulse width SCK logic low level pulse width Input signal rise/fall time CS setup time SCK setup time Data setup time Data hold time CS hold time SCK hold time CS standby pulse width CS output high impedance time SCK output data time Output data hold time WP setup time WP hold time HOLD setup time HOLD hold time HOLD output low impedance time HOLD output high impedance time Write cycle time SCK output low impedance time Symbol FCLK tCLHI tCLLO tRF tCSS tCLS tDS tDH tCSH tCLH tCPH tCHZ tV tHO tWPS tWPH tHS tHH tHLz tHHz tWC tCLZ 0 0 30 30 30 30 50 100 5 90 90 20 30 90 90 90 150 80 90 90 1 Conditions min typ max 5 Unit MHz ns ns us ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns
AC Characteristics (at FCLK = 3MHz)/VDD = 1.8V to 3.6V
Parameter Clock frequency SCK logic high level pulse width SCK logic low level pulse width Input signal rise/fall time CS setup time SCK setup time Data setup time Data hold time CS hold time SCK hold time CS standby pulse width CS output high impedance time SCK output data time Output data hold time WP setup time WP hold time HOLD setup time HOLD hold time HOLD output low impedance time HOLD output high impedance time Write cycle time SCK output low impedance time Symbol FCLK tCLHI tCLLO tRF tCSS tCLS tDS tDH tCSH tCLH tCPH tCHZ tV tHO tWPS tWPH tHS tHH tHLz tHHz tWC tCLZ 0 0 30 30 30 30 120 120 10 100 100 30 50 100 150 120 200 150 120 120 1 Conditions min typ max 3 Unit MHz ns ns us ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns
No.A1435-4/14
LE25LB2562M
Table 1 Command Settings
Command Write enable (WREN) Write disable (WRDI) Status register read (RDSR) Status register write (WRSR) Read (READ) Write (WRITE) Explanatory notes for Table 1 The "h" following each code indicates that the number given is in hexadecimal notation. Addresses A15 for all commands are "don't care." *1: "PD" stands for page program data. Any amount of data from 1 to 64 bytes is input. 1st bus cycle 06h 04h 05h 01h 03h 02h DATA A15-A8 A15-A8 A7-A0 A7-A0 PD *1 PD *1 PD *1 PD *1 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle nth bus cycle
Figure 2 Serial Input Timing
(SPI Mode 0)
tCPH
CS
tCLS tCSS tCLHI tCLLO tCSH tCLH
SCK
tDS tDH
SI
DATA VALID
SO
(SPI Mode 3)
High Impedance
High Impedance
tCPH
CS
tCLS tCSS tCLLO tCLHI tCSH tCLH
SCK
tDS tDH
SI
DATA VALID
SO
High Impedance
High Impedance
No.A1435-5/14
LE25LB2562M
Figure 3 Serial Output Timing
(SPI Mode 0)
CS
SCK
tCLZ tHO DATA VALID tV tCHZ
SO
SI
(SPI Mode 3)
CS
SCK
tCLZ tHO DATA VALID tV tCHZ
SO
SI
No.A1435-6/14
LE25LB2562M
Description of Commands and Their Operations
"Table 1 Command Settings" provides a list and overview of the commands. A detailed description of the functions and operations corresponding to each command is presented below.
1. Read (READ)
Consisting of the first through third bus cycles, the read command inputs the 16-bit addresses following (03h), and the data in the designated addresses is output synchronized to SCK. The data is output from SO on the falling edge of third bus cycle bit0 as a reference. "Figure 4 READ" shows the timing waveforms. When SCK is input continuously after the read command has been input and the data in the designated addresses has been output, the address is automatically incremented inside the device while SCK is being input, and the corresponding data is output in sequence. If the SCK input is continued after the internal address arrives at the highest address, the internal address returns to the lowest address (0000h), and data output is continued. By setting the logic level of CS to high, the device is deselected, and the read cycle ends. While the device is deselected, the output pin SO is in a high-impedance state.
Figure 4 READ
CS
Mode3 012345 678 15 16 23 24 25 26 27 28 29 30 31
SCK SI SO
Mode0 8CLK 03h
(00000011)
Add.
(A15-A8)
Add.
(A7-A0)
High Impedance
765432107 Data Out(N) Data Out(N+1)
* Addresses A15 are "don't care." * In synchronization with the rising edges of 0 to 23 clock signals, the command is identified and the addresses are taken in through SI. * In synchronization with the falling edges of 23 clock signal or later, the data is output to SO.
No.A1435-7/14
LE25LB2562M
2. Status Registers
The status registers read the operating and setting statuses inside the device from outside (status register read) and set the protect information (status register write). There are 8 bits in total, and "Table 2 Status Registers" gives the significance of each bit.
Table 2 Status Registers
Bit Bit0 Name RDY Logic 0 1 Bit1 WEN 0 1 Bit2 BP0 0 1 Bit3 BP1 0 1 Bit4 Bit5 Bit6 Bit7 x x x SRWP 0 0 0 0 1 Reserved bit Reserved bit Reserved bit Status register write enabled Status register write disabled Block protect information See status register description on BP0 and BP1 Function Ready Busy (in write operation) Write disabled Write enabled Nonvolatile information Nonvolatile information 0 0 0 Nonvolatile information 0 Power-on time Information 0
2-1. Status Register Read (RDSR)
The contents of the status registers can be read using the status register read command. This command can be executed even during write operation. "Figure 5 Status Register READ" shows the timing waveforms of status register read. Consisting only of the first bus cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit7) is the first to be output, and each time one clock is input, all the other bits up to RDY (bit0) are output in sequence, synchronized to the falling clock edge. If the clock input is continued after RDY (bit0) has been output, the data is output by returning to the bit (SRWP) that was first output, after which the output is repeated as long as the clock input is continued. The data can be read by the status register read command at any time.
Figure 5 Status Register Read
CS
Mode3 0 1 2 3 4 5 678 9 10 11 12 13 14 15
SCK SI SO
Mode0 8CLK 05h
(00000101)
Hight Impedance
765432107 Status Register Out
No.A1435-8/14
LE25LB2562M
2-2. Status Register Write (WRSR)
The information in status registers BP0, BP1, and SRWP can be rewritten using the status register write command. RDY, WEN, bit4, bit5, and bit6 are read-only bits and cannot be rewritten. The information in bits BP0, BP1, and SRWP is stored in the non-volatile memory, and when it is written in these bits, the contents are retained even at power-down. "Figure 6 Status Register Write" shows the timing waveforms of status register write, and Figure 11 shows a status register write flowchart. Consisting of the first and second bus cycles, the status register write command initiates the internal write operation at the rising CS edge after the data has been input following (01h). By the operation of this command, the information in bits BP0, BP1, and SRWP can be rewritten. Since bits RDY (bit0), WEN (bit1), bit4, bit5, and bit6 of the status register cannot be written, no problem will arise if an attempt is made to set them to any value when rewriting the status register. Status register write ends can be detected by RDY of status register read. Information in the status register can be rewritten 1,000 times (min.). To initiate status register write, the logic level of the WP pin must be set high and the status register WEN must be set to "1".
Figure 6 Status Register Write
Self-timed Write Cycle tSRW
CS
tWPS tWPH
WP
Mode3 012345678 15
SCK
Mode0 8CLK
SI
01h
(00000001)
DATA
SO
Hight Impedance
2-3. Contents of Each Status Register
RDY (bit0) Ready/Busy detection The RDY register is for detecting the write end. When it is "1", the device is in a busy state, and when it is "0", it means that the write operation is completed. WEN (bit1) Write enable The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will not perform the write operation even if the write command is input. If it is set to "1", the device can perform write operation in any area that is not block-protected. WEN can be controlled using the write enable and write disable commands. By inputting the write enable command (06h), WEN can be set to "1", and by inputting the write disable command (04h), it can be set to "0". In the following states, WEN is automatically set to "0" in order to protect against unintentional writing. * At power-on * Upon completion of write * Upon completion of status register write If a write operation has not been performed inside the device because, for instance, the command input for any of the write operations has failed or a write operation has been performed for a protected address, WEN will retain the status established prior to the issue of the command concerned. Furthermore, its state will not be changed by a read operation.
No.A1435-9/14
LE25LB2562M
BP0, BP1 (bits2, 3) Block Protect Settings Block protect BP0 and BP1 are status register bits that can be rewritten, and the memory space to be protected can be set depending on these bits. For the setting conditions, refer to "Table 3 Protect Level Setting Conditions."
Table 3 Protect Level Setting Conditions
Status Register Bits Protection Block (Level) 0 (Whole area unprotected) 1 (Upper 1/4 area protected) 2 (Upper 1/2 area protected) 3 (Whole area protected) BP1 0 0 1 1 BP0 0 1 0 1 Protected Area None 6000h to 7FFFh 4000h to 7FFFh 0000h to 7FFFh
SRWP (bit7) Status Register Write Protect Settings Status register write protect SRWP is the bit for protecting the status registers, and its information can be rewritten. When SRWP is "1" and the logic level of the WP pin is low, the status register write command is ignored, and status registers BP0, BP1, BP2, and SRWP are protected. When the logic level of the WP pin is high, the status registers are not protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 4 SRWP Setting Conditions."
Table 4 SRWP Setting Conditions
WP Pin 1 0 1 0 SRWP 0 0 1 1 Hardware protected (HPM) Protected Protected Unprotected Software protected (SPM) Unprotected Protected Unprotected Mode Status Register Protected Area Unprotected Area
Bit4, bit5, and bit6 are reserved bits, and have no significance.
3. Write Enable (WREN)
Before performing any of the operations listed below, the device must be placed in the write enable state. Operation is the same as for setting status register WEN to "1", and the state is enabled by inputting the write enable command. "Figure 7 Write Enable" shows the timing waveforms when the write enable operation is performed. The write enable command consists only of the first bus cycle, and it is initiated by inputting (06h). * Write (WRITE) * Status register write (WRSR)
4. Write Disable (WRDI)
The write disable command sets status register WEN to "0" to prohibit unintentional writing. "Figure 8 Write Disable" shows the timing waveforms. The write disable command consists only of the first bus cycle, and it is initiated by inputting (04h). The write disable state (WEN "0") is exited by setting WEN to "1" using the write enable command (06h).
Figure 7 Write Enable
CS
Mode3 01234567
Figure 8 Write Disable
CS
Mode3 01234567
SCK SI SO
Mode0 8CLK 06h
(00000110)
SCK SI SO
Mode0 8CLK 04h
(00000100)
High Impedance
High Impedance
No.A1435-10/14
LE25LB2562M
5. Write (WRITE)
The LE25LB2562M enables pages with up to 64bytes to be written. Any number of bytes from 1 to 64bytes can be written within the same sector page (page addresses : A15 to A6). "Figure 9 Write" shows the write timing waveforms, and Figure 12 shows a write flowchart. After the falling CS edge, the command (02H) is input followed by the 16-bit addresses (Add). The write data is then loaded until the rising CS edge, and the internal addresses (A5 to A0) are incremented (Add+1) every time the data is loaded in 1-byte increments. The data loading continues until the rising CS edge. If the data loaded has exceeded 64bytes, the 64bytes loaded last are written. The write data must be loaded in 1-byte increments, and the write operation is not performed at the rising CS edge occurring at any other timing. The write time is 10ms (max.) when 64bytes (1page) are written at one time.
Figure 9 Write
Self-timed Write Cycle tWC
CS
Mode3 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 535
SCK SI SO
Mode0 8CLK
02h
(00000010)
Add.
(A15-A8)
Add.
(A7-A0)
PD
(N)
PD
(N+1)
PD
(N+2)
PD
(N+63)
High Impedance
* Addresses A15 are "don't care."
6. Hold Function
Using HOLD pin, the hold function suspends serial communication (it places it in the hold status). "Figure 10 HOLD" shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the logic level of SCK is low, and it exits from the hold status at the rising HOLD edge. When the logic level of SCK is high, HOLD must not rise or fall. The hold function takes effect when the logic of CS is low, and the hold status is exited and serial communication is reset at the rising CS edge. In the hold status, the SO output is in the high-impedance state, and SI and SCK are "don't care."
Figure 10 HOLD
CS
Active
HOLD
Active
tHS
tHS
SCK
tHH tHH
HOLD
tHHZ tHLZ High Impedance
SO
No.A1435-11/14
LE25LB2562M
7. Hardware Data Protection
In order to protect against unintentional writing at power-on, the LE25LB1282 incorporates a power-on reset function.
8. Software Data Protection
This product eliminates the possibility of unintentional operations by not recognizing commands under the following conditions. * When a write command is input and the rising CS edge timing is not in a bus cycle (8CLK units of SCK). * When the write data is not in 1-byte increments. * When the status register write command is input for 2bus cycles or more.
9. Power-on
In order to protect against unintentional writing, CS must be kept at VDD at power-on. After power-on, the supply voltage has stabilized at 1.8V or higher, wait for 10s (tPU_READ) before inputting the command to start a read operation. Similarly, wait for 10ms (tPU_WRITE) after the supply voltage has stabilized at 1.8V or higher before inputting the command to start a write operation.
10. Decoupling Capacitor
A0.1F ceramic capacitor must be provided to each device and connected between VDD and VSS in order to ensure that the device will operate stably.
No.A1435-12/14
LE25LB2562M
Figure 11 Status Register Write Flowchart Figure 12 Write Flowchart
Status register write Start Set write enable command Write Start Set write enable command
06h
06h
01h Data
02h Set status register write command Address 1 Address 2 Set write command
Program start on rising edge of CS
Data 0 Set status register read command Data 1 Data n
05h
NO
Bit 0= "0" ? YES End of status register write Write start on rising edge of CS
Set status register read command
05h
*Automatically placed in write disabled state at the end of the status register write.
NO
Bit 0= "0" ? YES End of write *Automatically placed in write disabled state at the end of the write.
No.A1435-13/14
LE25LB2562M
Application Note
1) Precautions at Power-on In order to protect against unintentional writing, the LE25LB2562M incorporates a power-on rest circuit. The following conditions must be met in order to ensure that the power-on reset circuit will operate stably. No guarantees are given for data in the event of an instantaneous power failure occurring during the write operation.
Symbol tRISE tOFF Vbot Power rise time Power off time Power bottom voltage 10 0.2 Item min VDD = 1.8 to 3.6V typ max 100 ms ms V Unit
tRISE
VDD
tOFF Vbot
0V
Note: 1). The CS pin must be set high.
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This catalog provides information as of April, 2009. Specifications and information herein are subject to change without notice.
No.A1435-14/14

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